Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system. The design flow typically starts with a specification for a new circuit, which can be transformed into a logical design. The logical design can model the circuit at a register transfer level (RTL), which is usually coded in a Hardware Design Language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like.
The logical design typically utilizes a design hierarchy to describe the circuit in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. For example, when the circuit includes a processing system having multiple processing cores, rather than describe the entire processing system with each of the processing cores separately, i.e., in a flat representation, the logical design can describe a design unit for the processing core, which can be linked to multiple locations in a design unit for a processing system.
The typical technique for linking or interfacing the various design units is to include an instantiation statement in a higher-level design unit of the logical design, so that once design units have been compiled, the higher-level design unit can instantiate a lower-level design unit in response to execution of the instantiation statement. All too often, however, the inclusion of an instantiation statement in the higher-level design unit becomes impossible, as the higher-level design unit was purchased already-compiled with no access to the source code, or it may just be undesirable to modify the coding of the higher-level design unit. In these instances, the System Verilog hardware design language includes a bind command that can instantiate a lower-level design unit into a higher-level design unit without modifying the code of the higher-level design unit. The specific syntax of System Verilog bind commands and their associated usage can be found in of the IEEE Standard 1800-2005, section 17.15.
While these bind commands have become highly utilized, especially, to incorporate verification components into a logical design, they do have their limitations. For example, since the System Verilog hardware design language intends bind commands to be utilized in binding multiple System Verilog design units together, when the higher-level design unit is written is a different hardware design language, such as VHDL or System C, execution of the bind command creates a mixed language environment for the logical design. These mixed-language environments often do not support many of the features or expressions associated with bind commands, as the functionality associated with one hardware design language often differs from the functionality of a different hardware design language. This lack of full bind command functionality in mixed language environments often leads to errors during execution and re-design of the design units or the bind commands to ensure the design units properly interface after instantiation.